Semiconductor device

ABSTRACT

In the semiconductor device, a control power MOSFET chip  2  is disposed on the input-side plate-like lead  5,  and the drain terminal DT 1  is formed on the rear surface of the chip  2,  and the source terminal ST 1  and gate terminal GT 1  are formed on the principal surface of the chip  2,  and the source terminal ST 1  is connected to the plate-like lead for source  12.  Furthermore, a synchronous power MOSFET chip  3  is disposed on the output-side plate-like lead  6,  and the drain terminal DT 2  is formed on the rear surface of the chip  3  and the output-side plate-like lead  6  is connected to the drain terminal DT 2.  Furthermore, source terminal ST 2  and gate terminal GT 2  are formed on the principal surface of the synchronous power MOSFET chip  3,  and the source terminal ST 2  is connected to the plate-like lead for source  13.  The plate-like leads for source  12  and  13  are exposed, and therefore, it is possible to increase the heat dissipation capability of the MCM  1.

CROSS-REFERENCE TO RELATED APPLICATIONS

More than one reissue application has been filed for the reissue of U.S.Pat. No. 7,145,224. The reissue applications are application Ser. No.12/821,999 (the present application) and Ser. No. 12/130,782, now U.S.Pat. No. Re. 41,869, both of which are reissues of U.S. Pat. No.7,145,224.

CLAIM OF PRIORITY

Claim of priority the present application claims priority from Japaneseapplication serial no. 2004-020474, filed on Jan. 28, 2004, the contentof which is hereby incorporated by reference into this application.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor device, andspecifically to a technology which effectively applies to asemiconductor device in which a plurality of semiconductor chips areencapsulated in a sealed body.

In a conventional semiconductor device, the rear surface of a heat sink(first conductive member) is soldered on the upper surface of eachsemiconductor chip, and the upper surface of a second conductive memberis soldered on the rear surface of each semiconductor chip. Furthermore,the rear surface of a third conductive member is soldered on the uppersurface of the heat sink, and the land of the prescribed semiconductorchip has an electrical connection to a control terminal via a bondingwire. The semiconductor chips, heat sink, upper surface of the secondconductive member, rear surface of the third conductive member, and apart of the bonding wire and control terminal are encapsulated withinresin. Japanese Application Patent Laid-open Publication No.2002-110893, FIG. 1.

In the above semiconductor device, an external cooling member abuts onthe rear surface of the second conductive member with a plate-likeinsulating member interposed in order to accelerate the heatdissipation. See Japanese Application Patent Laid-open Publication No.2003-46036, FIG. 1.

SUMMARY OF THE INVENTION

Recently, semiconductor devices have been highly integrated and the sizeof the device has been reduced. Especially, a semiconductor device inwhich a plurality of semiconductor chips are encapsulated within aninsulating material is called a multi-chip-module (MCM) and is widelydeveloped.

One application of the above-mentioned MCM is a switching circuit usedfor a power-supply circuit. Among those, an insulated DC/DC converter iswidely used for information devices such as personal computers. Suchproducts are required to be highly efficient and small because centralprocessing units (CPU) are using larger current and higher frequency.

A DC/DC converter consists of two power MOSFETS (Metal OxideSemiconductor Field Effect Transistor), one for control and one forsynchronization, a driver IC (integrated circuit) for turning theMOSFETS on and off, and other components such as a choke coil andcapacitor. Generally, in an MCM for a DC/DC converter, two power MOSFETSand one driver IC are encapsulated in one package.

The objective of encapsulating a plurality of semiconductor chips in onepackage (sealed body) is to reduce the package area as well as reduceparasitic components such as parasitic inductances and resistanceslocated on the circuit.

Moreover, because a power-supply circuit uses large current and highfrequency, parasitic components cause significant power loss. To preventthat problem, it is necessary to shorten the wiring patterns betweenchips, between the driver IC and MOSFETS, and between the outputterminal and a load. In a power-supply MCM, a driver IC and MOSFETS arelocated near each other and encapsulated together, and semiconductorelements constituting a power-supply circuit are integrated in onepackage. This configuration allows the MCM to be mounted extremely closeto the load. Therefore, it is expected that the MCM will be the mostcommonly used power-supply device.

That is, when compared to a conventional packaging method in whichindividually-packaged elements are arrayed on a printed board, in theabove-mentioned MCM, the wiring distance is shorter and parasiticinductances and resistances are significantly reduced, thereby enablinga low-loss circuit.

Although, in an MCM, encapsulating a plurality of semiconductor chips inone package reduces the package area, there is a problem in that theheat dissipation capability is reduced.

Furthermore, as shown in a comparative example in FIG. 16 which theinventor of the present invention has been studying, in an MCM, wiresare used for major current paths between the chips and frame to enableelectrical connections. Therefore, wires make up a significant portionof all the parasitic components. As a result, there is a problem in thatparasitic components such as parasitic resistances and inductances inthose wires increase.

An objective of the present invention is to provide a semiconductordevice which is capable of improving the electrical characteristics.

Furthermore, another objective of the present invention is to provide asemiconductor device which is capable of improving the capability ofdissipating heat.

The above-mentioned and other objectives, and novel features will becomemore apparent as the description in this specification proceeds withreference to the accompanying drawings.

Major embodiments of the present invention disclosed in this applicationare briefly described as shown below:

That is, a semiconductor device according to the present inventioncomprises

a plurality of semiconductor chips, each of which has a terminal on itsprincipal surface,

a plate-like conductive member which has electrical connections to atleast two semiconductor chips' terminals among the plurality ofsemiconductor chips,

a sealed body which encapsulates the plurality of semiconductor chips,and

a plurality of external connection terminals which have individualelectrical connections to the plurality of semiconductor chips, wherein

the at least two semiconductor chips which are connected by theplate-like conductive member have an individual transistor circuit, andthe plate-like conductive member is exposed outside the sealed body.

Furthermore, a semiconductor device according to the present inventioncomprises

a plurality of semiconductor chips, each of which has a terminal on itsprincipal surface,

a plate-like conductive member which has electrical connections to atleast two semiconductor chips' terminals among the plurality ofsemiconductor chips,

a sealed body which encapsulates the plurality of semiconductor chips byresin, and

a plurality of external connection terminals which have individualelectrical connections to the plurality of semiconductor chips, wherein

the plate-like conductive member is exposed outside the sealed body, and

the connecting portion of the plate-like conductive member at which theplate-like conductive member is connected to one semiconductor chip isjoined to the connecting portion at which the plate-like conductivemember is connected to the other semiconductor chip, on either theprincipal or rear surface of the sealed body, or on the outside of thesemiconductor chips inside the sealed body.

Furthermore, a semiconductor device according to the present inventioncomprises

a plurality of semiconductor chips, each of which has a terminal on itsprincipal surface,

a plate-like conductive member which has electrical connections to atleast two semiconductor chips' terminals among the plurality ofsemiconductor chips,

a sealed body which encapsulates the plurality of semiconductor chips byresin, and

a plurality of external connection terminals which have individualelectrical connections to the plurality of semiconductor chips and aredisposed on the peripheral edge of the rear surface of the sealed body,wherein

the plate-like conductive member is exposed on the at least eitherprincipal or rear surface of the sealed body.

Furthermore, in a semiconductor device according to the presentinvention, a plurality of semiconductor chips are encapsulated, wherein

major current paths between elements or between terminals and elementshave electrical connections made possible by a plate-like conductor, and

at least three conductors having different potentials are partiallyexposed on either the upper or rear surface of the semiconductor device,or on both surfaces.

Furthermore, in a semiconductor device according to the presentinvention,

a plurality of semiconductor chips are connected in series by aplate-like conductor, and a plurality of semiconductor chips areconnected to the same surface of the conductor, wherein

among a plurality of semiconductor chips consisting of the semiconductordevice,

one or more semiconductor chips are disposed upside down andencapsulated.

For an example, in an MCM for a DC/DC converter,

the control power MOSFET chip's drain terminal has an electricalconnection to the input terminal, which is an external connectionterminal, via a plate-like conductor, or is directly connected to aplate-like conductor which is a part of the input terminal, andsimilarly,

the synchronous power MOSFET chip's source terminal has an electricalconnection to the ground terminal, which is an external connectionterminal, via a plate-like conductor, or is directly connected to aplate-like conductor which is a part of the ground terminal.

Furthermore, the control power MOSFET chip's source terminal and thesynchronous power MOSFET chip's drain terminal are individuallyconnected to plate-like conductors, and the plate-like conductors areconnected to each other by a certain conductor, or the control powerMOSFET chip's source terminal and the synchronous power MOSFET chip'sdrain terminal are connected to a part of a common conductor.

Furthermore, the conductor has an electrical connection to the outputterminal which is an external connection terminal, or is a part of theoutput terminal.

Furthermore, a plate-like conductor which is connected to the inputterminal, ground terminal and output terminal or is a part of theterminals is partially or entirely exposed outside the insulatingmaterial which encapsulates the semiconductor device.

Furthermore, a common plate-like conductor is used to connect thecontrol power MOSFET chip's source terminal and the synchronous powerMOSFET chip's drain terminal, and the synchronous power MOSFET isconnected upside down to the common surface of the conductor.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view, seen through a sealed body, showing an example ofthe structure of a semiconductor device (multiple chip module for anon-insulated DC/DC converter) according to embodiment 1 of the presentinvention;

FIG. 2 is a cross-sectional view showing the cross-sectional structuretaken substantially along the lines A-A in FIG. 1;

FIG. 3 is a drawing of the rear surface showing the structure of thesemiconductor device shown in FIG. 1;

FIG. 4 is an outside perspective view showing the structure of thesemiconductor device shown in FIG. 1;

FIG. 5 is a cross-sectional view showing the structure of asemiconductor device which is an altered example according to embodiment1 of the present invention;

FIG. 6 is a cross-sectional view showing the structure of asemiconductor device which is an altered example according to embodiment1 of the present invention;

FIG. 7 s a cross-sectional view showing the structure of a semiconductordevice which is an altered example according to embodiment 1 of thepresent invention;

FIG. 8 is a circuit diagram showing an example of an equivalent circuitwhen the MCM 1 shown in FIG. 1 is mounted on the semiconductor device(non-insulated DC/DC converter);

FIG. 9 is a plan view, seen through a sealed body, showing an example ofthe structure of a semiconductor device (multiple chip module for anon-insulated DC/DC converter) according to embodiment 2 of the presentinvention;

FIG. 10 is a cross-sectional view showing the cross-sectional structuretaken substantially along the lines B-B in FIG. 9:

FIG. 11. is a drawing of the rear surface showing the structure of thesemiconductor device shown in FIG. 9.

FIG. 12 is an outside perspective view showing the structure of thesemiconductor device shown in FIG. 9;

FIG. 13 is a cross-sectional view showing an example of the structure ofa semiconductor device (multiple chip module for a non-insulated DC/DCconverter) according to embodiment 3 of the present invention;

FIG. 14 is a cross-sectional view showing the structure of asemiconductor device which is an altered example according to embodiment3 of the present invention;

FIG. 15 is a plan view, seen through a sealed body, showing an exampleof the structure of a semiconductor device (multiple chip module for anon-insulated DC/DC converter) according to embodiment 4 of the presentinvention;

FIG. 16 is a plan view, seen through a sealed body, showing thestructure of a power-supply multiple chip module which is a comparativeexample; and

FIG. 17 is a perspective view, seen through a sealed body, showing theinside of the semiconductor device shown in FIG. 1.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following embodiments, the same or similar parts will not berepeatedly described unless specifically necessary.

Furthermore, as a matter of convenience, in the following embodiments, aplurality of separate sections or embodiments will be explained whennecessary. However, those separate sections or embodiments are allrelated unless otherwise specified, and one section may be a part of orthe whole of an altered example, or a description may be a detailed orsupplementary explanation.

Moreover, in the following embodiments, when the number of elements(including the number of items, numeric value, quantity, and range) ismentioned, the number of elements is not limited to a specific numberand could be more or less unless otherwise specified, or unless thenumber of elements is obviously limited to a specific number inprinciple.

Hereafter, embodiments of the present invention will be explained indetail with reference to the drawings. In all of the drawings used forexplaining the embodiments, members that have the same function havebeen assigned the same numbers to avoid repeated explanations.

(Embodiment 1)

FIG. 1 is a plan view, seen through a sealed body, showing an example ofthe structure of a semiconductor device (multiple chip module for anon-insulated DC/DC converter) according to embodiment 1 of the presentinvention. FIG. 17 is a perspective view, seen through a sealed body,showing the inside of the semiconductor device shown in FIG. 1. FIG. 2is a cross-sectional view showing the cross-sectional structure takensubstantially along the lines A-A in FIG. 1. FIG. 3 is a drawing of therear surface showing the structure of the semiconductor device shown inFIG. 1. FIG. 4 is an outside perspective view showing the structure ofthe semiconductor device shown in FIG. 1. FIGS. 5 through 7 arecross-sectional views showing the structure of a semiconductor devicewhich is an altered example according to embodiment 1 of the presentinvention. FIG. 8 is a circuit diagram showing an example of anequivalent circuit when the MCM 1 shown in FIG. 1 is mounted on thesemiconductor device (non-insulated DC/DC converter). FIG. 16 is a planview, seen through a sealed body, showing the structure of apower-supply multiple chip module which is a comparative example.

In a semiconductor device according to embodiment 1, shown in FIGS. 1through 4 and 17, a plurality of semiconductor chips are encapsulated inone sealed body (insulating resin for sealing) 17. In embodiment 1, anMCM (multiple chip module) 1 for a non-insulated DC/DC converter isexplained as one example of the above-mentioned semiconductor device.

Furthermore, as shown in FIG. 3, an MCM 1 has a non-leaded QFN (QuadFlat Non-leaded Package) structure in which a plurality of externalconnection terminals 11 are disposed on the peripheral edge of the rearsurface 17b of the sealed body 17.

The MCM 1 according to embodiment 1 basically consists of a plurality ofsemiconductor chips, a plate-like conductive member which has electricalconnections to at least two semiconductor chips' terminals among thosesemiconductor chips, a sealed body 17 which encapsulates the pluralsemiconductor chips, and a plurality of external connection terminals 11disposed on the peripheral edge of the rear surface 17b of the sealedbody 17. Furthermore, in the MCM 1, at least two semiconductor chipsconnected by the plate-like conductive member have an individualtransistor circuit, and the plate-like conductive member is exposedoutside the sealed body 17.

Moreover, the MCM 1 has a control power MOSFET chip 2 (firstsemiconductor chip), a synchronous power MOSFET chip 3 (secondsemiconductor chip) which has an electrical connection in series to thecontrol power MOSFET chip 2 by a plate-like conductive member, and adriver IC chip 4 (third semiconductor chip) which turns on and off thosesemiconductor chips. The three semiconductor chips are sealed(encapsulated) in the sealed body 17.

That is, the MCM 1 has two semiconductor chips (first and secondsemiconductor chips) each of which has a power-supply transistorcircuit, and one semiconductor chip (third semiconductor chip) which hasa driver circuit for controlling the two semiconductor chips.

The detailed structure of the MCM 1 according to embodiment 1 will beexplained. As shown in FIGS. 1 and 2, a control power MOSFET chip (firsttransistor) 2 is disposed on the input-side plate-like lead (firstplate-like conductive member) 5. That is, a terminal which functions asa drain terminal DT1 (first output electrode) of the control powerMOSFET is formed on the rear surface 2b of the control power MOSFET chip2, and the input-side plate-like lead 5 which is a first plate-likeconductive member is connected to the drain terminal DT1.

On the principal surface 2a of the control power MOSFET chip 2,terminals which function as the control power MOSFET chip's sourceterminal (second output electrode) ST1 and gate terminal (inputelectrode) GT1 are formed, and the source terminal ST1 located on theprincipal surface 2a of the control power MOSFET chip 2 is connected tothe plate-like lead for source 12 which is a second plate-likeconductive member.

Furthermore, a synchronous power MOSFET chip (second transistor) 3 isdisposed on the output-side plate-like lead 6. That is, a terminal whichfunctions as a drain terminal (first output terminal) DT2 of thesynchronous power MOSFET is formed on the rear surface 3b of thesynchronous power MOSFET chip 3, and the output-side plate-like lead 6which is a third plate-like conductive member is connected to the drainterminal DT2. On the principal surface 3a of the synchronous powerMOSFET chip 3, terminals which function as the synchronous power MOSFETchip's source terminal ST2 and gate terminal (input electrode) GT2 areformed, and the source terminal ST2 located on the principal surface 3aof the synchronous power MOSFET chip 3 is connected to the plate-likelead for source 13 which is a fourth plate-like conductive member.

Furthermore, the MCM 1 has a ground-side plate-like lead 7 and adriver-side plate-like lead 8, and a driver IC chip 4 is disposed on thedriver-side plate-like lead 8. That is, the driver IC chip 4 and thedriver-side plate-like lead 8 are connected to each other. On the driverIC chip 4, some terminals 9 among a plurality of terminals 9 located onthe principal surface 4a of the driver IC chip 4 are electricallyconnected to the power MOSFET chips' gate terminal GT1, source terminalST1, gate terminal GT2 and source terminal ST2 by wires 10, such as goldwires or thin metal wires, thereby the power MOSFETS are turned on andoff.

Other terminals 9 located on the principal surface 4a of the driver ICchip 4 are a power supply voltage terminal, boot terminal, voltage checkterminal and a control signal input terminal, and each of the terminalsis connected to a corresponding external connection terminal 11 by awire 10.

As shown in FIG. 3, the input-side plate-like lead 5, output-sideplate-like lead 6, and driver-side plate-like lead 8, each of which hasan installed semiconductor chip, are partially or entirely exposed onthe rear surface 17b of the sealed body 17 of the MCM 1. Those leadsfunction as external connection terminals that have electricalconnections to the printed wiring board as well as function as heatradiating parts that dissipates heat on the printed wiring board.

As FIGS. 1 and 2 show, the plate-like lead for source 12 provides anelectrical connection between the source terminal ST1 of the controlpower MOSFET chip 2 and the output-side plate-like lead 6. Similarly,the plate-like lead for source 13 provides an electrical connectionbetween the source terminal ST2 of the synchronous power MOSFET chip 3and the ground-side plate-like lead 7.

Moreover, as FIG. 4 shows, the plate-like lead for source 12 and theplate-like lead for source 13 are partially exposed on the upper surface17a of the sealed body 17 of the MCM 1.

Furthermore, as FIG. 2 shows, drain terminals DT1 and DT2 located on therear surfaces 2b and 3b of the control power MOSFET chip 2 and thesynchronous power MOSFET chip 3 are joined to the input-side plate-likelead 5 and the output-side plate-like lead 6, respectively, with diebonding material, such as silver paste 14, interposed.

On the other hand, source terminals ST1 and ST2 located on the principalsurfaces 2a and 3a of the control power MOSFET chip 2 and thesynchronous power MOSFET chip 3 are joined to the plate-like leads forsource 12 and 13, respectively, via a plurality of protruding conductiveelectrodes such as gold bumps 15.

It is possible to use protruding solder electrodes or paste-likeconductive adhesives to join the source terminals ST1 and ST2 located onthe principal surfaces 2a and 3a of the control power MOSFET chip 2 andthe synchronous power MOSFET chip 3, respectively, to the plate-likeleads for source 12 and 13.

FIGS. 2, 5, 6 and 7 show various types of connections between the secondplate-like conductive member and the third plate-like conductive member,and between the fourth plate-like conductive member and the ground-sideplate-like lead 7.

As shown in FIG. 2, the plate-like lead for source 12 has an electricalconnection to the output-side plate-like lead 6 via a conductor 16, andthe plate-like lead for source 13 has an electrical connection to theground-side plate-like lead 7 via a conductor 16. Furthermore, as shownin an altered example in FIG. 5, it is possible to create the portionsbetween the plate-like leads for source 12a and 13a and the connectionsto the output-side plate-like lead 6 and the ground-side plate-like lead7, respectively, so that those portions become the same conductivemembers as the leads and then provide electrical connections by usingsolder 18. A conductive member (second conductive member or thirdconductive member) which consists of a plate-like lead for source 12,conductor 16, and an output-side plate-like lead 6 has two bends whichforms a nearly S-shape.

Furthermore, as shown in altered examples in FIGS. 6 and 7, it ispossible to integrate the plate-like lead for source (second plate-likeconductive member) 12 and the output-side plate-like lead (thirdplate-like conductive member) 6, and also integrate the plate-like leadfor source 13 and the ground-side plate-like lead 7. In an alteredexample shown in FIG. 6, leads are integrated by press work. In analtered example shown in FIG. 7, leads are integrated by bending work.

Thus, in the MCM 1 according to embodiment 1, the plate-like lead forsource 12 located on the upper-surface 17a side of the sealed body 17 isjoined and electrically connected to the output-side plate-like lead 6located on the rear surface 17b side of the sealed body 17, on theoutside of the control power MOSFET chip 2 and the synchronous powerMOSFET chip 3, inside the sealed body 17.

Next, FIG. 8 shows an example of an equivalent circuit when the MCM 1 ismounted. The MCM 1 is connected by a coil 20, capacitors 22 and 23, load24 and an input power source 21 by wires. In a non-insulated DC/DCconverter circuit 19, heat is mostly generated by the control powerMOSFET chip 2 and the synchronous power MOSFET chip 3.

According to an MCM 1 of embodiment 1, one surface of the plate-likeconductive member which functions as a current path is connected to asemiconductor chip and the other surface is exposed outside the sealedbody 17, thereby making it possible to increase the capability ofdissipating heat. The plate-like conductive member exposed on the rearsurface 17b of the sealed body 17 functions as an external connectionterminal and is also capable of dissipating heat on the printed wiringboard where the MCM 1 is mounted. Furthermore, the plate-like conductivemember exposed on the upper surface 17a of the sealed body 17 directlydissipates heat in the ambient air or increases the heat conductivity toa heat radiating member, such as a heat radiating fin 27 (see FIGS. 13and 14) or heat sink, mounted on the MCM 1.

That is, heat generated by the control power MOSFET chip 2 and thesynchronous power MOSFET chip 3 is conveyed from the input-sideplate-like lead 5 and the output-side plate-like lead 6, which areexposed on the rear surface 17b of the sealed body 17, to the printedwiring board, thereby dissipating the heat. Furthermore, heat can beexternally dissipated from the plate-like lead for source 12 and theplate-like lead for source 13 which are exposed on the upper surface 17aof the sealed body 17, thereby increasing the heat dissipationcapability.

As a result, it is possible to increase the heat dissipation capabilityin the MCM 1. It is also possible to increase the voltage conversionefficiency of the MCM 1.

Furthermore, in an MCM 1 according to embodiment 1, the source terminalST1 of the control power MOSFET chip 2 is connected to the output-sideplate-like lead 6 by the plate-like leads for source 12, and the sourceterminal ST2 of the synchronous power MOSFET chip 3 is connected to theground-side plate-like lead 7 by the plate-like leads for source 13.Therefore, when compared to a multiple chip module in a comparativeexample, shown in FIG. 16, which uses ordinary wire connections usingwires 25 such as gold wires, the cross-sectional area of the currentpath can be made larger in the MCM 1 according to embodiment 1. As aresult, parasitic components, such as parasitic resistances andinductances, are reduced, which makes it possible to increase theconversion efficiency.

That is, it is possible to reduce parasitic resistances and parasiticinductances compared to the situations where wire connections are used,thereby making it possible to increase the electrical characteristics ofthe MCM 1.

Furthermore, it is possible to easily manufacture a reliablesemiconductor device by connecting in series the current path betweenthe first transistor's first output electrode and second outputelectrode to the current path between the second transistor's firstoutput electrode and second output electrode, and mechanicallyintegrating the first, second and third conductive members, and firstand second transistors.

(Embodiment 2)

FIG. 9 is a plan view, seen through a sealed body, showing an example ofthe structure of a semiconductor device (multiple chip module for anon-insulated DC/DC converter) according to embodiment 2 of the presentinvention. FIG. 10 is a cross-sectional view showing the cross-sectionalstructure taken substantially along the lines B-B in FIG. 9. FIG. 11 isa drawing of the rear surface showing the structure of the semiconductordevice shown in FIG. 9. FIG. 12 is an outside perspective view showingthe structure of the semiconductor device shown in FIG. 9.

Similar to embodiment 1, a semiconductor device according to embodiment2 is an MCM (multiple chip module) 1 for a non-insulated DC/DCconverter. The semiconductor device is a semiconductor package in whicha control power MOSFET chip 2, synchronous power MOSFET chip 3 and adriver IC chip 4 which turns on and off those power MOSFET chips areencapsulated.

The structure of the MCM 1 according to embodiment 2 will be described.As FIGS. 9 and 10 show, a control power MOSFET chip 2 is disposed on aninput-side plate-like lead 5. And, terminals which function as thecontrol power MOSFET chip's source terminal ST1 and gate terminal GT1are formed on the principal surface 2a of the control power MOSFET chip2. Furthermore, a terminal which functions as the control power MOSFETchip's drain terminal DT1 is formed on the rear surface 2b of thecontrol power MOSFET chip 2.

On the other hand, what is different from embodiment 1 is that asynchronous power MOSFET chip 3 is disposed on the ground-sideplate-like lead 7. That is, as shown in FIG. 10, the synchronous powerMOSFET chip 3, which is a second semiconductor chip, is disposedreversely (principal and rear surfaces upside down) compared to thecontrol power MOSFET chip 2 which is a first semiconductor chip.Moreover, a terminal which functions as the synchronous power MOSFETchip's drain terminal DT2 is formed on the principal surface 3a of thesynchronous power MOSFET chip 3, and terminals which function as thesynchronous power MOSFET chip's source terminal ST2 and gate terminalGT2 are formed on the rear surface 3b of the synchronous power MOSFETchip 3.

As FIG. 9 shows, the MCM 1 for a DC/DC converter has an output-sideplate-like lead 6.

Furthermore, a driver IC chip 4 is disposed on the driver-sideplate-like lead 8. Some of the terminals 9 located on the principalsurface 4a of the driver IC chip 4 have electrical connections to thecontrol power MOSFET chip's 2 gate terminal GT1 and source terminal ST1,and the synchronous power MOSFET chip's 3 source terminal ST2 and gateterminal GT2, thereby turning on and off each power MOSFET. Moreover,because the gate terminal GT2 is downwardly formed on the principalsurface 3a, as shown in FIG. 9, some of the terminals 9 of the driver ICchip 4 are connected to the synchronous power MOSFET chip's 3 gateterminal GT2 by wires 10 with a metal plate 26 interposed. The gateterminal GT2 has an electrical connection to a metal plate 26 via bumpelectrodes, for example. Other terminals are a power supply voltageterminal, boot terminal, voltage check terminal, and a control signalinput terminal. Each of the terminals is connected to a correspondingexternal connection terminal 11 by a wire 10.

As shown in FIG. 11, the input-side plate-like lead 5, output-sideplate-like lead 6, ground-side plate-like lead 7 and driver-sideplate-like lead 8 are partially or entirely exposed on the rear surface17b of the sealed body 17. Thus, those plate-like leads function asexternal connection terminals which have electrical connections to theprinted wiring board as well as function as heat radiating parts whichdissipate heat on the printed wiring board.

However, it is not necessary to expose all of the plate-like leads. Forexample, it is possible that only the output-side plate-like lead 6 ishidden.

Furthermore, the plate-like lead for source 12 provides electricalconnections between the source terminal ST1 of the control power MOSFETchip 2 and the drain terminal DT2 of the synchronous power MOSFET chip3. As shown in FIG. 12, the plate-like lead for source 12 is partiallyexposed on the upper surface 17a of the sealed body 17.

Therefore, in an MCM 1 according to embodiment 2, as shown in FIG. 9,the connecting portion of the plate-like lead for source 12 (secondplate-like conductive member) at which the lead connects to the controlpower MOSFET chip 2 (one semiconductor chip) is joined to the connectingportion at which the lead connects to the synchronous power MOSFET chip3 (the other semiconductor chip) on the upper surface 17a of the sealedbody 17.

Moreover, the surface of the control power MOSFET chip 2 on which thedrain terminal DT1 is formed is pressure-bonded to the input-sideplate-like lead 5, for example, via a die bonding material such assilver paste 14, and the source terminal ST1 located on the oppositesurface is connected to the plate-like lead for source 12, for example,via a conductive material such as a gold bump 15.

On the other hand, the surface of the synchronous power MOSFET chip 3 onwhich the drain terminal DT2 is formed is pressure-bonded to theplate-like lead for source 12, for example, via a die bonding materialsuch as silver paste 14, and the source terminal ST2 located on theopposite surface is connected to the ground-side plate-like lead 7, forexample, via a conductive material such as a gold bump 15.

In an MCM 1 according to embodiment 2, by installing at least onesemiconductor chip upside down, it is possible to make manufacturing ofthe plate-like lead for source 12 much easier than that of an MCM 1according to embodiment 1. That is, as shown in FIG. 10, it is possibleto connect the source terminal ST1 of the control power MOSFET chip 2and the drain terminal DT2 of the synchronous power MOSFET chip 3 ontothe same surface of the plate-like lead for source 12 by using only oneplate-like lead for source 12. Therefore, it is possible to avoid thecomplicated manufacturing process in which a plurality of semiconductorchips are connected on the different surfaces of the plate-like lead forsource 12. As a result, it is possible to reduce the time to connect andmanufacture leads. Thus, the structure of the MCM 1 can be simplified.

Furthermore, because the plate-like lead for source 12 can be formed byusing only one plate-like lead, it is possible to make the area of theplate-like lead for source 12 larger than that of the MCM 1 according toembodiment 1. As a consequence, the heat dissipation capability can beincreased and the voltage conversion efficiency can also be increased.

(Embodiment 3)

FIG. 13 is a cross-sectional view showing an example of the structure ofa semiconductor device (multiple chip module for a non-insulated DC/DCconverter) according to embodiment 3 of the present invention. FIG. 14is a cross-sectional view showing the structure of a semiconductordevice which is an altered example according to embodiment 3 of thepresent invention.

Similar to embodiments 1 and 2, a semiconductor device according toembodiment 3 is an MCM (multiple chip module) 1 for a non-insulatedDC/DC converter. The structure which will increase the heat dissipationcapability will be explained.

An MCM 1 shown in FIG. 13 is an MCM 1 in which a heat radiating fin 27(heat radiating member) is mounted to the MCM 1 according toembodiment 1. That is, in an MCM 1 according to embodiment 1, twoplate-like leads (plate-like leads for source 12 and 13) exposed on theupper surface 17a of the sealed body 17 have different potentials, andtherefore, a heat radiating member such as a heat radiating fin 27 isinstalled with an insulating sheet 28 interposed.

Thus, by mounting a heat radiating fin 27 to the plate-like lead exposedon the upper surface 17a of the MCM 1, it is possible to increase theheat dissipation capability of the MCM 1.

Furthermore, an MCM 1 shown in FIG. 14 is an MCM 1 in which a heatradiating fin 27 (heat radiating member) is mounted to the MCM 1according to embodiment 2. In this MCM 1, only one plate-like lead forsource 12 is exposed on the upper surface 17a of the sealed body 17.Therefore, the plate-like lead for source 12 can be directly connectedto the heat radiating fin 27 without an insulating sheet 28 interposed.Consequently, it is possible to make the heat dissipation capabilityhigher than that of the MCM 1 shown in FIG. 13.

Furthermore, it is also possible to integrate the plate-like lead forsource 12 and the heat radiating fin 27, thereby making it possible toincrease the heat dissipation capability.

(Embodiment 4)

FIG. 15 is a plan view, seen through a sealed body, showing an exampleof the structure of a semiconductor device (multiple chip module for anon-insulated DC/DC converter) according to embodiment 4 of the presentinvention.

Similar to embodiments 1 and 2, a semiconductor device according toembodiment 4 is an MCM (multiple chip module) 1 for a non-insulatedDC/DC converter. In an MCM 1 according to embodiments 1 and 2, wires 10are used to connect the control power MOSFET chip's 2 source terminalST1 and gate terminal GT1 to the driver IC chip's 4 terminals 9, or toconnect the synchronous power MOSFET chip's 3 source terminal ST2 andgate terminal GT2 to the driver IC chip's 4 terminals 9. However, in anMCM 1 according to embodiment 4, metal plates (other plate-likeconductive members) 29 are used for the connections of the gate drivecircuits, or other connections.

That is, in an example shown in FIG. 15, the terminal of the controlpower MOSFET chip 2 has an electrical connection to a correspondingterminal 9 of the driver IC chip 4 by a metal plate 29, and the terminalof the synchronous power MOSFET chip 3 also has an electrical connectionto a corresponding terminal 9 of the driver IC chip 4 by a metal plate29. Furthermore, electrical connections between the terminals and metalplates 29 are provided, for example, by using gold bumps 15.

In the MCM 1, when the high-speed switching is selected, parasiticresistances and parasitic inductances, including a gate drive circuit,other than the main current path may cause the efficiency to decrease.Therefore, by connecting the driver IC chip 4 to the electrodes of thecontrol power MOSFET chip 2 and synchronous power MOSFET chip 3 by usingmetal plates 29, it is possible to reduce the parasitic resistances andparasitic inductances compared to the situations where wire connectionsare used.

Moreover, other connections that use wires 10 as shown in FIG. 15 can bereplaced with metal plates 29.

As stated above, the present invention provided by the inventor has beenexplained in detail according to the embodiments. However, the presentinvention is not intended to be limited to the above-mentionedembodiments, and can be embodied in a variety of forms as long as theydo not depart from the concept of the present invention.

For example, in the above embodiments 1 through 4, the MCM 1 which is aQFN-type semiconductor device is explained. However, the MCM 1 is notintended to be limited to the QFN-type semiconductor device, and can bea semiconductor device of other structures such as a QFP (Quad FlatPackage) type semiconductor device as long as a plurality ofsemiconductor chips are encapsulated in a sealed body. Furthermore, thenumber of encapsulated semiconductor chips is not intended to be limitedto three, therefore, there can be four or more semiconductor chips.

The present invention is suitable for use in a semiconductor device orelectronic device.

A major embodiment of the present invention disclosed in thisapplication is briefly described as shown below:

Because the present invention has a plate-like conductive member toconnect terminals of two semiconductor chips, it is possible to reduceparasitic resistances and parasitic inductances compared to thesituations where wire connections are used, thereby increasing theelectrical characteristics of the semiconductor device. Furthermore, theabove-mentioned plate-like conductive member is exposed outside thesealed body, thereby making it possible to increase the heat dissipationcapability of the semiconductor device.

1. A semiconductor device comprising a first transistor and a secondtransistor, each of which has an input electrode, first output electrodeand second output electrode, wherein the current path connecting betweensaid first output electrode and said second output electrode of saidfirst transistor are connected in series to the current path connectingbetween said first output electrode and said second output electrode ofsaid second transistor; either said first output electrode or saidsecond output electrode of said first transistor is connected to a firstconductive member; and the other output electrode of said firsttransistor is connected to a second conductive member; either said firstoutput electrode or said second output electrode of said secondtransistor is connected to said second conductive member; the otheroutput electrode of said second transistor is connected to a thirdconductive member; said first conductive member, said second conductivemember and said third conductive member are electrically isolated fromone another; and said first conductive member, said second conductivemember, said third conductive member, said first transistor and saidsecond transistor are mechanically integrated.
 2. A semiconductor deviceaccording to claim 1, wherein said second conductive member has two ormore bends.
 3. A semiconductor device according to claim 1, wherein saidsecond conductive member is a nearly S-shape.
 4. A semiconductor deviceaccording to claim 1, wherein in said second conductive member, thesurface to which an output electrode of said first transistor isconnected is located on the same side of the surface to which an outputelectrode of said second transistor is connected.
 5. A semiconductordevice comprising a plurality of semiconductor chips, each of which hasa terminal on its principal surface, a conductive plate which haselectrical connections to at least two semiconductor chips' terminalsamong said plurality of semiconductor chips, a sealed body whichencapsulates said plurality of semiconductor chips, and a plurality ofexternal connection terminals which have individual electricalconnections to the plurality of semiconductor chips, wherein at leasttwo semiconductor chips which are connected by the conductive plate havean individual transistor circuit, and the conductive plate is exposedoutside said sealed body.
 6. A semiconductor device according to claim5, wherein among said plurality of semiconductor chips, each of a firstsemiconductor chip and a second semiconductor chip has a power-supplytransistor circuit; and said semiconductor device further comprising afirst conductive plate which connects to a drain terminal of said firstsemiconductor chip, a second conductive plate which connects to a sourceterminal of said first semiconductor chip, a third conductive platewhich connects to a drain terminal of said second semiconductor chip,and a fourth conductive plate which connects to a source terminal ofsaid second semiconductor chip, wherein said second conductive plate hasan electrical connection to said third conductive plate, and said secondand third conductive plates are at least partially exposed outside saidsealed body.
 7. A semiconductor device according to claim 6, whereinsaid second conductive plate and said third conductor plate areintegrated.
 8. A semiconductor device according to claim 5, whereinamong said plurality of semiconductor chips, each of a firstsemiconductor chip and a second semiconductor chip has a power-supplytransistor circuit, and a third semiconductor chip has a driver circuitwhich controls said first and second semiconductor chips.
 9. Asemiconductor device according to claim 6, wherein said second andfourth conductive plates are partially exposed on either the principalor rear surface of said sealed body, and said first and third conductiveplates are partially exposed on the other surface of said sealed body.10. A semiconductor device according to claim 9, wherein said secondconductive plate and said third conductor plate are integrated.
 11. Asemiconductor device according to claim 5, wherein among said pluralityof semiconductor chips, at least one semiconductor chip is installedupside down in relation to the other semiconductor chips.
 12. Asemiconductor device according to claim 6, wherein said secondsemiconductor chip is installed upside down in relation to said firstsemiconductor chip, said second and third conductive plates arepartially exposed on either the principal or rear surface of said sealedbody; and said first and fourth conductive plates are partially exposedon the other surface of said sealed body.
 13. A semiconductor deviceaccording to claim 12, wherein said second conductive plate and saidthird conductive plate are integrated.
 14. A semiconductor deviceaccording to claim 5, wherein a heat radiating member is installed inthe exposed area of said conductive plate exposed outside said sealedbody.
 15. A semiconductor device comprising a plurality of semiconductorchips, each of which has a terminal on its principal surface, aconductive plate which has electrical connections to at least twosemiconductor chips' terminals among said plurality of semiconductorchips, a sealed body which encapsulates said plurality of semiconductorchips by resin, a plurality of external connection terminals which haveindividual electrical connections to the plurality of semiconductorchips, wherein said conductive plate is exposed outside said sealedbody, and the connecting portion of said conductive plate at which saidconductive plate is connected to one semiconductor chip is joined to theconnecting portion at which said conductive plate is connected to theother semiconductor chip, on either the principal or rear surface ofsaid sealed body, or on the outside of said semiconductor chips insidesaid sealed body.
 16. A semiconductor device according to claim 15,wherein among said plurality of semiconductor chips, each of a firstsemiconductor chip and a second semiconductor chip has a power-supplytransistor circuit, and a third semiconductor chip has a driver circuitwhich controls said first and second semiconductor chips.
 17. Asemiconductor device according to claim 15, wherein a heat radiatingmember is installed in the exposed area of said conductive plate exposedoutside said sealed body.
 18. A semiconductor device according to claim15, wherein said conductive plate has an electrical connection to thesemiconductor chip via a plurality of gold bumps.
 19. A semiconductordevice according to claim 16, wherein the terminal of said firstsemiconductor chip has an electrical connection to the terminal of saidthird semiconductor chip by said conductive plate, and the terminal ofsaid second semiconductor chip has an electrical connection to theterminal of said third semiconductor chip by another conductive plate.20. A semiconductor device comprising a plurality of semiconductorchips, each of which has a terminal on its principal surface, aconductive plate which has electrical connections to at least twosemiconductor chips' terminals among said plurality of semiconductorchips, a sealed body which encapsulates said plurality of semiconductorchips by resin, a plurality of external connection terminals which haveindividual electrical connections to said plurality of semiconductorchips and are disposed on the peripheral edge of the rear surface ofsaid sealed body, wherein said conductive plate is exposed on the atleast either principal or rear surface of said sealed body.
 21. Asemiconductor device according to claim 20, wherein among said pluralityof semiconductor chips, each of a first semiconductor chip and a secondsemiconductor chip has a power-supply transistor circuit, and a thirdsemiconductor chip has a driver circuit which controls said first andsecond semiconductor chips.
 22. A semiconductor device according toclaim 20, wherein a heat radiating member is installed in the exposedarea of said conductive plate exposed outside said sealed body.
 23. Asemiconductor device according to claim 20, wherein said conductiveplate has an electrical connection to the semiconductor chip via aplurality of gold bumps.
 24. A semiconductor device according to claim20, wherein among said plurality of semiconductor chips, each of a firstsemiconductor chip and a second semiconductor chip has a power-supplytransistor circuit, and said second semiconductor chip is installedupside down compared to said first semiconductor chip; and saidsemiconductor device further comprising a first conductive plate whichconnects to a drain terminal of said first semiconductor chip, a secondconductive plate which connects to a source terminal of said firstsemiconductor chip, a third conductive plate which connects to a drainterminal of said second semiconductor chip, and a fourth conductiveplate which connects to a source terminal of said second semiconductorchip, wherein said second and third conductive plates are partiallyexposed on either the principal or rear surface of said sealed body, andsaid first and fourth conductive plates are partially exposed on theother surface of said sealed to body.
 25. A semiconductor device for aDC/DC converter formed in a single package comprising: a firstsemiconductor chip having a main face and a rear face and electricallyconnected to a first conductor member at an input side; a secondsemiconductor chip having a main face and a rear face and electricallyconnected to a second conductor member at a grounding side, wherein thefirst and second semiconductor chips are arranged in opposite relationto one another with respect to the main faces and the rear facesthereof; a driver IC chip for controlling the first and secondsemiconductor chips; a source terminal formed in the main face of thefirst semiconductor chip; a drain terminal formed in the rear face ofthe first semiconductor chip; a drain terminal formed in the main faceof the second semiconductor chip; a source terminal and gate terminalformed in the rear face of the second semiconductor chip; a sourceterminal and gate terminal formed in a rear face of the secondsemiconductor chip; and a single conductor member formed above thesource terminal of the first semiconductor chip and the drain terminalof the second semiconductor chip; wherein the single conductor member iselectrically connected to the source terminal of the first semiconductorchip and the drain terminal of the second semiconductor chip, andwherein the gate terminal of the second semiconductor chip iselectrically connected to the driver IC chip.
 26. The semiconductordevice for a DC/DC converter according to claim 25, wherein the firstsemiconductor chip and the second semiconductor chip are powertransistors.
 27. A semiconductor device for a DC/DC converter formed ina single package comprising: a first external terminal; a secondexternal terminal; a third external terminal; a first semiconductorchip, having a main face and a rear face and formed above the firstexternal terminal, electrically connected to a first conductor member atan input side; a second semiconductor chip, having a main face and arear face and formed above the second external terminal, electricallyconnected to a second conductor member at a grounding side; a driver ICchip for controlling the first and second semiconductor chips; a sourceterminal formed in the main face of the first semiconductor chip; adrain terminal formed in the rear face of the first semiconductor chip,wherein the first and second semiconductor chips are arranged inopposite relation with respect to the main and rear faces thereof; adrain terminal formed in the main face of the second semiconductor chip;a source terminal and a gate terminal formed in the rear face of thesecond semiconductor chip; and a single conductor member formed abovethe source terminal of the first semiconductor chip, the drain terminalof the second semiconductor chip and the third external terminal;wherein the single conductor member is electrically connected to thesource terminal of the first semiconductor chip, the drain terminal ofthe second semiconductor chip and the third external terminal, wherein aterminal is formed in a main face of the driver IC chip, wherein a wireis connected to the terminal of the driver IC chip and the gate terminalof the second semiconductor chip, wherein the first, second and thirdexternal terminals are formed in a rear face of the package, and whereinthe first external terminal is electrically connected to the drainterminal of the first semiconductor chip.
 28. The semiconductor devicefor a DC/DC converter according to claim 27, wherein a gate terminal isformed in the main face of the first semiconductor, wherein a secondterminal different from the terminal formed in the main face of thedriver IC chip is formed in the main face of the driver IC chip, andwherein a wire is connected to the second terminal of the driver ICchip.
 29. The semiconductor device for a DC/DC converter according toclaim 27, wherein a cross sectional area of the conductor plate memberis larger than that of the wire.
 30. The semiconductor device for aDC/DC converter according to claim 29, wherein the first and secondsemiconductor chips are power transistors.
 31. A semiconductor devicefor a DC/DC converter formed in a single package comprising: a plateconductor member at an input side; a plate conductor member at agrounding side; a plate conductor member at an output; a firstsemiconductor chip having a main face and a rear face and formed abovethe first external terminal and electrically connected to a plateconductor member at an input side; a second semiconductor chip having amain face and a rear face and formed above the second external terminaland electrically connected to a plate conductor member at a groundingside, wherein the first and second semiconductor chips are arranged inopposite relation with respect to the main and rear faces thereof; asource terminal and a gate terminal formed in the main face of the firstsemiconductor chip; a drain terminal formed in the rear face of thefirst semiconductor chip; a drain terminal formed in the main face ofthe second semiconductor chip; a source terminal formed in the rear faceof the second semiconductor chip; and a single conductor member formedabove the plate conductor member at the output side, the source terminalof the first semiconductor chip and the drain terminal of the secondsemiconductor chip and the third external terminal wherein the singleconductor member is electrically connected to the source terminal of thefirst semiconductor chip, the drain terminal of the second semiconductorchip and the plate conductor member at the output side, a wireelectrically connected to the source terminal of the secondsemiconductor chip; wherein the plate conductor members at the inputside, grounding side and output side are formed in the rear face of thepackage, wherein the plate conductor member at the input side iselectrically connected to the drain terminal of the first semiconductorchip, and wherein the plate conductor member at the grounding side iselectrically connected to the source terminal of the secondsemiconductor chip.
 32. The semiconductor device for a DC/DC converteraccording to claim 31, wherein cross sectional areas of the conductorplate members are each respectively larger than that of the wire. 33.The semiconductor device for a DC/DC converter according to claim 31,which further comprises a driver IC chip for controlling the first andsecond semiconductor chips, wherein the source terminal of the firstsemiconductor chip is electrically connected to the driver IC chip. 34.The semiconductor device for a DC/DC converter according to claim 31,wherein the source terminal of the first semiconductor chip iselectrically connected to an area where the conductor plate member atthe output side is not connected, and wherein the wire is connected tothe area.
 35. A semiconductor device for a DC/DC converter formed in asingle package comprising: a plate conductor member at an input side; aplate conductor member at a grounding side; a plate conductor member atan output side; a first semiconductor chip having a main face and a rearface and formed above the conductor member at input side; a secondsemiconductor chip having a main face and a rear face and above theplate conductor member at the grounding side, wherein the first andsecond semiconductor chips are arranged in opposite relation withrespect to the main and rear faces thereof; a source terminal and a gateterminal formed on the main surface of the first semiconductor chip, adrain terminal formed on the rear face of the first semiconductor chip;a drain terminal formed on the main face of the second semiconductorchip; a source terminal formed on the rear face of the secondsemiconductor chip; a single conductor member above the plate conductormember at the output side, wherein the single conductor member iselectrically connected to the source terminal of the first semiconductorchip, the drain terminal of the second semiconductor chip, and the plateconductor member at the output side; and a wire connected to the sourceterminal of the first semiconductor chip; wherein the plate conductormember at the input side, the plate conductor member at the groundingside and the plate conductor member at the output side are formed in arear face of the package, wherein the plate conductor member at theinput side is electrically connected to the drain terminal of the firstsemiconductor chip, and wherein the plate conductor member at thegrounding side is electrically connected to the source terminal of thesecond semiconductor chip.
 36. The semiconductor device for a DC/DCconverter according to claim 35, which further comprises a driver ICchip for controlling the first and second semiconductor chips, whereinthe gate terminal of the first semiconductor is electrically connectedto the driver IC chip, and wherein a wire is electrically connected tothe driver IC chip.
 37. The semiconductor device for a DC/DC converteraccording to claim 35, which further comprises a driver IC chip forcontrolling the first and second semiconductor chips, wherein a gateterminal of the second semiconductor chip is formed in the rear face ofthe second semiconductor chip, and wherein the gate terminal of thesecond semiconductor chip is electrically connected to the driver ICchip.
 38. The semiconductor device according to claim 35, wherein thefirst semiconductor chip and the second semiconductor chip are powertransistors.
 39. A semiconductor device for a DC/DC converter formed ina single package comprising: a first semiconductor chip having a mainface and a rear face and electrically connected to a plate conductormember; a second semiconductor chip having a main face and a rear faceand electrically connected to a plate conductor member at a groundingside; a source terminal and a gate terminal formed on the main surfaceof the first semiconductor chip, a drain terminal formed in the rearface of the first semiconductor chip; a drain terminal formed in themain face of the second semiconductor chip; a source terminal formed inthe rear face of the second semiconductor chip; and a single conductormember above the source terminal of the first semiconductor chip and thedrain terminal of the second semiconductor chip, wherein the singleconductor member is electrically connected to the source terminal of thefirst semiconductor chip and the drain terminal of the secondsemiconductor chip, and wherein a wire is connected to the sourceterminal and the gate terminal of the first semiconductor chip.
 40. Asemiconductor device for a DC/DC converter formed in a single packagecomprising: a first semiconductor chip having a main face and a rearface and electrically connected to a plate conductor member; a secondsemiconductor chip having a main face and a rear face and electricallyconnected to a plate conductor member at a grounding side; a driver ICchip for controlling the first and second semiconductor chips; a sourceterminal and a gate terminal formed on the main surface of the firstsemiconductor chip, a drain terminal formed on the rear face of thefirst semiconductor chip; a drain terminal formed in the main face ofthe second semiconductor chip; a source terminal formed in the rear faceof the second semiconductor chip; and a single conductor member abovethe source terminal of the first semiconductor chip and the drainterminal of the second semiconductor chip, wherein the single conductormember is electronically connected to the source terminal of the secondsemiconductor chip, and wherein a wire is connected to the sourceterminal of the first semiconductor chip and the driver IC chip.
 41. Thesemiconductor device for a DC/DC converter according to claim 40,wherein the wire is connected to a source terminal area where the singleconductor member is not connected to the first semiconductor chip.
 42. Asemiconductor device for a DC/DC converter comprising: a firstsemiconductor chip having a main face and a rear face and electricallyconnected to a plate conductor member at an input side; a secondsemiconductor chip having a main face and a rear face and connected to aplate conductor member at a grounding side, wherein the first and secondsemiconductor chips are arranged in opposite relation with respect tothe main and rear faces thereof; a driver IC chip for controlling thefirst and second semiconductor chips; a source terminal formed in themain face of the first semiconductor chip; a drain terminal formed inthe rear face of the first semiconductor chip; a drain terminal formedin the main face of the second semiconductor chip; a source terminalformed in the rear face of the second semiconductor chip; and a singleconductor member formed above the source terminal of the firstsemiconductor chip and drain terminal of the second semiconductor chip,wherein the single conductor member is electrically connected to thesource terminal and the gate terminal of the first semiconductor chip,and wherein the driver IC chip is provided with a terminal to connectwith the source terminal of the first semiconductor chip.
 43. Thesemiconductor device according to claim 42, wherein the wire iselectrically connected to the terminal of the driver IC chip in an areaof the source terminal where the first semiconductor chip is notconnected to the single conductor member.
 44. The semiconductor devicefor a DC/DC converter according to claim 42, wherein a gate terminal isformed in the main face of the first semiconductor chip, and a wire forelectrically connecting the driver IC chip is connected to the gateterminal.
 45. The semiconductor device for a DC/DC converter accordingto claim 42, wherein a gate terminal is formed in the rear face of thesecond semiconductor chip, and the gate terminal of the secondsemiconductor chip is electrically connected to the terminal of thedriver IC chip.
 46. The semiconductor device for a DC/DC converteraccording to claim 42, wherein a sectional area of the plate conductormember at the output side is larger than that of the wire.
 47. Thesemiconductor device according to claim 25, wherein the first and secondconductor members are plate conductor members.
 48. The semiconductordevice according to claim 27, wherein the first and second conductormembers are plate conductor members.